The 74HC595 is an 8-bit serial-in/parallel-out shift register with a storage latch and 3-state outputs — the standard way to turn three MCU pins into eight outputs.
Its 16 pins split into three jobs: data movement (A, SRCLK, SRCLR, SQ_H), output control (RCLK, OE), and the eight outputs (Q_A–Q_H) plus power.
Most 595 failures are wiring, not silicon — in the Arduino forum posts we track, the top two causes are an OE pin left floating and an RCLK pin never connected.
Learn the three groups and the chip becomes predictable.
| Pin | Name | Type | Function |
|---|---|---|---|
| 1–7 | Q_B–Q_H | Output | Parallel outputs 1–7 (3-state) |
| 8 | GND | Power | Ground |
| 9 | SQ_H | Output | Serial output — feeds the next chip's A in a chain |
| 10 | SRCLR | Input | Shift register clear, active-low — tie HIGH for normal operation |
| 11 | SRCLK | Input | Shift clock — data moves on the rising edge |
| 12 | RCLK | Input | Latch clock — rising edge copies shift register to outputs |
| 13 | OE | Input | Output enable, active-low — tie LOW to enable outputs |
| 14 | A | Input | Serial data input |
| 15 | Q_A | Output | Parallel output 0 (3-state) |
| 16 | VCC | Power | Supply, 2.0V–6.0V |
The SQ_H trap: pin 9 looks like just another output, but it is the serial output — it mirrors the last shifted bit, not the latched Q_H state. Wiring a display to SQ_H instead of Q_H is a classic first-build mistake.
| Parameter | Value |
|---|---|
| Type | 8-bit serial-in / parallel-out shift register + latch + 3-state outputs |
| Supply Voltage | 2.0V to 6.0V |
| Outputs | Q_A–Q_H (3-state) + SQ_H serial |
| Propagation Delay | 26ns typical (MC74HC595A A-suffix) |
| Quiescent Current | 4µA typical |
| Output Drive | 15 LSTTL loads; ~8mA per pin |
| Shift Frequency | ~100MHz class at 5V |
| Operating Temperature | -55°C to +125°C |
| Packages | SOIC-16, TSSOP-16, PDIP-16, SOEIAJ-16 |
| Compliance | Pb-free, halogen-free, RoHS (MC74HC595A per ON Semi datasheet Rev 23) |
A single 595 drives the seven segments plus decimal point of one digit — eight outputs, three MCU pins. Shift the segment pattern in, pulse RCLK, and the digit holds its display while the MCU does something else. Multi-digit displays chain another 595 per digit and multiplex the common cathodes.
Why 330Ω per segment: at 5V with a ~2V LED drop, each resistor limits the segment to about 9mA — safely inside the 595’s ~8mA-per-pin class and bright enough for bench work. One shared resistor would make digit brightness depend on how many segments are lit.
1. OE (pin 13) left floating. The outputs stay disabled and nothing ever appears. OE is active-low — tie it to GND, or drive it when you want to blank the display.
2. SRCLR (pin 10) not tied high. The shift register sits in reset and data never loads. Tie it to VCC unless you actually need the clear function.
3. RCLK (pin 12) never connected. Data shifts in but never latches — the classic "only works when I touch the chip" case, where a finger provides the missing clock signal.
4. No decoupling capacitor. One 0.1µF ceramic per chip, VCC to GND. Missing caps cause glitches and — in one documented ESP32 build — a 595 failing after two days of operation.
5. Daisy-chain order confusion. In a 16-bit chain, the first bit shifted is the last bit out — wiring segments in the wrong order makes "all outputs flash at once" until the byte order is fixed.
6. Expecting PWM dimming. The 595 is digital; it cannot vary LED brightness. Dim through PWM on the outputs (via transistors) or a dedicated LED driver.
7. shiftOut() argument mistakes. Passing integers instead of byte bit-patterns produces garbage on the pins. Use byte values like 0b10101010 with LSBFIRST/MSBFIRST chosen to match the wiring.
ICMASS stocks 74HC595-family parts in 16-pin packages — MC74HC595ADTR2G (TSSOP-16) and related variants, with same-day dispatch from Shenzhen. Contact us for a quote on your specific quantity and package preference.
A: 1–7 = Q_B–Q_H, 8 = GND, 9 = SQ_H, 10 = SRCLR, 11 = SRCLK, 12 = RCLK, 13 = OE, 14 = A, 15 = Q_A, 16 = VCC. The eight outputs Q_A–Q_H are the parallel port; SQ_H is the serial-out pin for cascading.
A: It is the serial output — it passes the overflow bit to the next 595’s data input in a daisy chain. It mirrors the shifted data, not the latched outputs, so do not wire a display to it expecting Q_H behavior.
A: OE to GND (active-low enable), SRCLR to VCC (active-low clear). Left floating, OE disables all outputs and SRCLR keeps the register reset — the two most common causes of a "dead" 595.
A: You are providing the missing latch clock — connect RCLK (pin 12). The shift register clocks data in on SRCLK, but the outputs update only on the RCLK rising edge; without it, your finger’s capacitance is the latch pulse.
A: SQ_H (pin 9) to the next chip’s A (pin 14), with SRCLK and RCLK shared across all chips. Each chip adds eight outputs. Remember the bit order: the first byte shifted ends up in the last chip.
A: Yes — one 0.1µF ceramic between VCC and GND on every chip. Chained registers share switching transients; missing decoupling shows up as glitches and, in documented cases, premature chip failure.
A: Yes — about 8mA per pin, with one series resistor per LED. For brighter segments or higher-current loads, buffer with transistors or move to the TPIC6B595 open-drain class (150mA per channel).
A: Volume pricing typically ranges from $0.03–$0.08/unit depending on brand and quantity. ICMASS stocks 74HC595-family parts in SOIC, TSSOP, and PDIP-16 and ships same-day from Shenzhen. Contact us for a quote.





