The 18A part and the 15A part in the same 30V SO-8 family share the same 7mΩ — and neither can actually carry its rated current on the board in front of you. Nameplate amps are 25°C promises, and the fine print decides the real envelope.
From what we see across Shenzhen lots (2025–2026), the 30V SO-8 class is a volume socket: cordless tool boards, appliance load switches, small inverters, and UPS sections. It's also the class where selection mistakes repeat — bigger die numbers bought for loads they never see.
This guide walks the selection the way a design review would: the thermal envelope, the gate-drive row, the die trade-offs, the avalanche question, and the honest "don't use any of these" cases.
The headline current of a power MOSFET is measured at a 25°C case — or worse, a 25°C ambient — with the test board carrying the heat. The NCE 30V family shows the pattern across three dies.
Per the three official datasheets, the derating is the first honest number: NCE3010S drops from 10A to 7A at 100°C; NCE3015S from 15A to 10.6A; NCE3018AS from 18A to 12.7A. The package envelopes tell the same story: 2.5W, 3.5W, and 3W maximum dissipation.
Work the conduction math from the RDS(on) max rows — no measurement needed, just P = I²R:
| Part | RDS(on) max @ 10V | Loss at its headline current | Envelope share |
|---|---|---|---|
| NCE3010S (10A) | 12mΩ | 10A → 1.2W | 48% of 2.5W |
| NCE3015S (15A) | 7mΩ | 15A → 1.58W | 45% of 3.5W |
| NCE3018AS (18A) | 7mΩ | 18A → 2.27W | 76% of 3.0W |
The 18A part burns three-quarters of its envelope in conduction before switching loss, before hot spots, before anything else. That's what "18A" costs.
An SO-8 MOSFET has no metal tab and no heatsink hole. Its junction-to-ambient path runs through the lead frame into the PCB copper — which means the datasheet thermal number is only as good as your layout.
The family's RθJA rows — 50°C/W for the 10A part, 36 for the 15A, 42 for the 18A — carry a footnote that changes everything: they're measured on FR4 for t ≤ 10 seconds.
Steady state runs hotter. Fairchild's AN-1032 puts a minimal-copper SO-8 near 125°C/W; good drain copper with vias brings real-world numbers toward the 60-80°C/W range.
Why does the footnote matter? Because steady state is where your board lives — and steady state runs hotter than the sticker.
The design consequence: two parts with the same RDS(on) run at the same temperature at the same current — the 15A and 18A dies are thermally twins on your board. Copper, not die size, separates them.
A practical rule from the numbers: ≥100mm² of drain copper and several thermal vias is the rated operating condition, not an optimization. On a skimpy pour, honest continuous envelopes land near 5-7A, 8-12A, and 10-14A for the three family steps.
Every MOSFET turns on at its threshold — but the threshold is where conduction begins, not where it's cheap. The row that matters is RDS(on) at your actual gate voltage, and this family's rows flip the die ranking.
| Part | VGS(th) max | RDS(on) max @ 4.5V | 4.5V row test current |
|---|---|---|---|
| NCE3010S | 3.0V | 16mΩ | 5A |
| NCE3015S | 2.4V | 9.5mΩ | — |
| NCE3018AS | 1.4V | 10mΩ | 10A |
On a 5V-logic rail the 15A middle die is the family's best buy — lowest 4.5V row at the lowest gate charge. The 18A top die has the lowest threshold but a worse 4.5V row; threshold margin and guaranteed conduction are different promises.
The 3.3V question is the same everywhere: none of these parts spec RDS(on) below 4.5V. Forum guidance is consistent — a 3.3V rail needs a 2.5V-specified part or a gate driver, not hope.
From what we see in Shenzhen (2025–2026), 5V-logic boards keep blowing or cooking their 10A-class switches and migrate up the family without checking the 4.5V row. The row that saves them is the one nobody quotes.
RDS(on) at 10V drops from 12mΩ (10A) to 7mΩ (15A) — then stops. The 18A top die shares the 15A part's 7mΩ. Stepping past the middle die buys no conduction performance at all.
| Rating | NCE3010S | NCE3015S | NCE3018AS |
|---|---|---|---|
| ID continuous @ 25°C | 10A | 15A | 18A |
| IDM pulsed | 50A | 60A | 72A |
| Qg total | 32.5nC | 32.3nC | 41nC |
| EAS single pulse | not published | 120mJ | 204mJ (conditions) |
The 18A part charges 27% more gate per cycle (41nC vs 32.3nC) and costs more. What it buys is the event table: 72A pulse for hot-plug inrush, and a published avalanche budget with test conditions for stall kicks.
Why does the gate-charge tax matter? Because it's paid on every switching cycle — and because a 27% delta that's trivial for a driver is exactly what a weak GPIO at frequency notices. Match the die to the stress, not the reel label.
Unclamped inductive loads put the MOSFET into avalanche at turn-off: the drain voltage rises past breakdown and the die absorbs the stored energy. If you don't clamp, you're betting on a datasheet number.
The family's numbers: the 10A entry publishes none; the 15A part publishes 120mJ; the 18A part publishes 204mJ with its test conditions (Tj 25°C, VDD 15V, L = 0.5mH, Rg = 25Ω). Conditions matter because EAS shrinks as the die heats — the 25°C number is the best case.
The design check is one line of math: a 2mH motor winding at 12A stores ½LI² = 144mJ. Against the 15A part's 120mJ that's already over budget at 25°C; against the 18A part's 204mJ it fits with derating room. That's the difference between a datasheet bet and a design.
Two honest caveats: EAS is single-pulse — repeated stall-recovery needs a repetitive rating (the AOS AO4410's EAR 135mJ is the class example) or a clamp. And a clamp diode beats avalanche every time when the board has room for one — avalanche is the budget for the events you can't clamp.
The family's honest limits, from the same datasheets:
The five-question fit check: questions 2 and 4 — the copper envelope and the event budget — are where most wrong selections fail.
Conduction loss at each part's headline current — calculated from RDS(on) max (P = I²R):
Gate charge per switching cycle — the driver's recurring cost:
Conduction loss at the nameplate current tells you the thermal job; gate charge tells you the driver job. Both matter more than the amp sticker.
From what we see in Shenzhen (2025–2026), the boards that fail selection do it at questions two and four — the copper envelope and the event budget. The die number is rarely the problem; the promises around it are.
A: Yes — same 7mΩ max means same conduction loss at the same current. The 18A part adds the 72A pulse and the 204mJ avalanche budget, not cooler running. At 15A on good copper, both sit at about 1.58W of conduction loss; the difference shows up at 18A, at hot-plug, or at stall.
A: Not by specification. RDS(on) rows stop at 4.5V on all three parts. The 18A part's 0.7-1.4V threshold gives the best margin — but margin isn't a guarantee, and forum guidance is consistent: 3.3V systems belong on 2.5V-specified parts or through a driver.
A: ≥100mm² of drain-side copper plus several thermal vias as the starting point. That's what makes the datasheet envelopes reachable. On minimal copper, SO-8 steady-state thermal resistance climbs toward 125°C/W and the honest continuous current collapses to a fraction of the nameplate.
A: Compare your stored energy against the derated value. Estimate ½LI² at the worst-case stall current, then de-rate for junction temperature — EAS is tested at 25°C. The 3018AS publishes its test conditions; the 15A part's 120mJ has none published, so give it more margin.
A: Hot-plug inrush and short-circuit transients. When a load with capacitor banks connects to a live rail, the charging current can hit tens of amps for milliseconds — inside the 72A pulse window but far past continuous capability. The pulse rating is the budget for that event.
A: The one your load actually stresses — we stock all three from the NCE factory line. Send us load current, gate drive, stall energy, and board copper and we'll confirm the die. Every lot is batch-tested at both drive points before shipping.





