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Q: Where are pins 1 through 8 on the NCE30P30G?

On the datasheet figure - and we verify them for you. The v1.0 package drawing (page 1, top and bottom views) shows pad numbering next to the role letters. This guide intentionally does not print a number map from memory. Send us your footprint and we confirm it against the NCE drawing before you commit copper.

Q: How do I test the part on the bench without a number map?

Use the body diode to identify source and drain. In diode mode, a P-ch reads conduction from source to drain through the body diode (one polarity only). Once the roles are found, the gate is the pad that shows capacitance to both. Then confirm against the figure.

Q: How do I verify a genuine NCE30P30G?

Measure RDS(on) at 10V/-15A and the threshold. A genuine part reads within 10mΩ max with VGS(th) in the -1.0 to -2.2V band, and its marking matches the datasheet. A relabeled smaller die fails the milliohm check at the -15A test current.

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NCE30P30G Pinout, Specifications & Common Mistakes | ICMASS

2026/9/8 21:31:50

The NCE30P30G is a -30V/-30A P-Channel power MOSFET in DFN5×6-8L — eight leadless pads plus a large exposed pad, 10mΩ max at 10V, 81.3nC gate charge, from Wuxi NCE Power (datasheet v1.0).

This is the 30P family's first DFN5×6-8L pinout guide — and the first thing to say about it is honest: the pad map must be verified against the datasheet figure before layout.

Here's what we can state from the datasheet schematic and what you must confirm on the drawing: pad roles — source, gate, drain — and the exposed-pad connection — are shown in the figure; numeric pad-by-pad assignment needs a look at the same figure with your layout engineer.

Why does this guide refuse to print pin numbers from memory? Because a wrong number in a pinout page is worse than no number.

We verify pad maps against the datasheet figure for every lot we ship — send us your footprint and we will confirm it before volume orders.

NCE30P30G Pin Diagram — Pad Roles

Pad Role	What It Carries	Notes
Source (S) pads	High-side connection — ties to the rail being switched	P-ch conducts from source to drain; in a high-side load switch the source sits at BAT+
Gate (G) pad	Drive signal from the gate network	±20V max — gate-to-source, never to logic ground alone
Drain (D) pads	Switched output and the current return of the die	Parallel pads share the drain current; all tie to the same net
Exposed pad (center)	Drain net and the main heat path	The pad is the rating — 80W case envelope lives here

Numeric pad assignment: the datasheet's package figure (top and bottom views) shows pad numbering alongside the role letters.

We do not print a per-pad number map on this page — because a wrong number in a pinout guide is worse than no number. Confirm the assignment on the datasheet figure (v1.0, page 1), then lock it in your footprint library.

If you are mid-layout, send us your pad map — we verify it against the NCE drawing before you commit copper.

Read this map as roles, not numbers: single gate pad, the remaining pads split between source and drain, and the center pad on the drain net. The numeric assignment lives on the datasheet figure — verify it, then lock it.

Key Specifications of NCE30P30G

Parameter	Value (datasheet v1.0)
Type / Package	P-Channel trench MOSFET / DFN5×6-8L
V_DS / V_GS	-30V / ±20V max
I_D @ T_C 25°C / I_DM	-30A / -160A pulsed
R_DS(on) max	10mΩ @ 10V (tested -15A); 15mΩ @ 4.5V (tested -10A)
V_GS(th)	-1.0 to -2.2V (typ -1.5V)
P_D / R_θJC	80W / 1.56°C/W
Q_g / C_iss	81.3nC / 4222pF
T_J	-55 to +150°C
100% UIS / ΔV_DS tested	Claimed; no E_AS row published

Three numbers drive every design decision here: 10mΩ at 10V (measurement at -15A), 81.3nC of gate, and a 1.56°C/W case path that only exists if the pad is soldered to copper.

What does the 80W case envelope actually require? A pad soldered to copper that moves the heat — nothing less.

The two drive rows of the NCE30P30G (datasheet v1.0):

R_DS(on) max @ 10V (tested -15A)10mΩ

R_DS(on) max @ 4.5V (tested -10A)15mΩ

Both rows are pulse tests at currents well below the -30A sticker. Test at the datasheet points, not at the sticker — that is where a counterfeit or a tired die shows.

Typical Application Circuit — High-Side Load Switch (Role-Level)

Role-level wiring: source-side pads to BAT+, drain-side pads and the exposed pad to the load's copper, gate pad through R_g to the drive network. The pad numbers come from the datasheet figure — the roles come from the schematic.

The pull-up must reference the source rail. On a 24V rail, clamp gate-source with an 18V zener — V_GS max is ±20V.

Common Mistakes When Using NCE30P30G

Mistake 1: Trusting a pad map from memory instead of the figure. Leadless 5x6 parts look alike; assignments do not always follow. One 10-second check on the datasheet page-1 drawing prevents a dead board.

Mistake 2: Soldering the exposed pad blind. The pad carries the drain and the heat — an unwetted pad means a part that runs hot and reads high R_DS(on). X-ray or electrical check after reflow; a grid stencil (70-75% open) keeps voids out of the joint.

Mistake 3: Hand-rework on a big copper pour without preheat. The copper that cools the part sinks your hot-air heat; DFN5×6 parts on large planes need a preheated board or hot plate — a real, forum-documented failure mode.

Mistake 4: Driving the gate from logic ground logic. P-ch turns off only when gate sits at source potential. Pull up to BAT+, not to ground — otherwise the switch stays on through MCU resets.

Mistake 5: Testing R_DS(on) at the sticker current. The 10mΩ row is guaranteed at -15A, not -30A. Test at the datasheet point or you will chase a ghost.

Mistake 6: Measuring in-circuit without a known-good pad map. Probe source and drain through the diode (body diode conducts one way only) to identify roles before you trust a fixture.

Frequently Asked Questions

Q1: Where are pins 1 through 8 on the NCE30P30G?

A: On the datasheet figure — and we verify them for you. The v1.0 package drawing (page 1, top and bottom views) shows pad numbering next to the role letters. This guide intentionally does not print a number map from memory. Send us your footprint and we confirm it against the NCE drawing before you commit copper.

Q2: Is the exposed pad the drain?

A: Yes — the exposed pad sits on the drain net and carries the heat. That is the family convention shown in the datasheet schematic, and it is why the pad-to-copper joint is a thermal component, not a mechanical detail. Solder it to 2oz copper with plugged vias.

Q3: Can I drop the NCE30P50G into the same footprint?

A: Both are DFN5×6 leadless bodies — but verify the pin map per figure before trusting one layout. Package family is not pin identity. Compare the two datasheets' top-view figures; when in doubt, ask us to verify both against your land pattern.

Q4: How do I rework this part without killing it?

A: Preheat the board, then use more time and less temperature. Big copper pours sink heat and make reflow hard — the classic DFN5×6 complaint. Preheat the assembly (hot plate or toaster-oven reflow) and keep the hot-air dwell short; check the pad wetting after.

Q5: How much do solder voids actually matter?

A: A lot — voids above ~35% can raise thermal resistance by 18-22%. The exposed pad is most of the junction-to-board path. A grid stencil aperture (70-75% open) vents the gas and keeps voiding in single digits.

Q6: How do I test the part on the bench without a number map?

A: Use the body diode to identify source and drain. In diode mode, a P-ch reads conduction from source to drain through the body diode (one polarity only). Once the roles are found, the gate is the pad that shows capacitance to both. Then confirm against the figure.

Q7: How do I verify a genuine NCE30P30G?

A: Measure R_DS(on) at 10V/-15A and the threshold. A genuine part reads within 10mΩ max with V_GS(th) in the -1.0 to -2.2V band, and its marking matches the datasheet. A relabeled smaller die fails the milliohm check at the -15A test current.