The M24128-BWMN6TP is a 128Kbit I²C EEPROM — the part that holds calibration data, serial numbers, and factory settings on a two-wire bus. Most boards change it for one of three reasons: cost, second-source security, or a 1MHz bus that a 400kHz part can't keep up with.
The replacement candidates are the Microchip AT24C128 and the onsemi CAT24C128 — both pin-compatible 24C128-family parts with the same 8-pin layout.
From what we see across Shenzhen lots (2025–2026), the swap itself never fails — what fails is firmware that assumed 1MHz at 3.3V, or a WC pin wired differently.
| Parameter | M24128-BWMN6TP (ST) | AT24C128 (Microchip) | CAT24C128 (onsemi) |
|---|---|---|---|
| Density | 128Kbit | 128Kbit | 128Kbit |
| Interface | I²C | I²C | I²C |
| Supply Voltage | 2.5V–5.5V | 1.7V–5.5V (AT24C128C) | 1.8V–5.5V |
| Max Clock | 1MHz at all voltages | 1MHz @ 5V; 400kHz @ 2.7V | 1MHz (Fast-Plus) |
| Page Size | 64 bytes | 64 bytes | 64 bytes |
| Write Cycle | 5ms | 5ms | 5ms |
| Endurance | >4 million cycles | 1 million cycles | 1 million cycles |
| Data Retention | >200 years | 100 years | 100 years |
| On-Chip ECC | Yes | No | Yes |
| Access Time | 450ns | ~600ns | 400ns |
| Write Protection | WC pin | WP pin | WP pin |
| Device Address | 0x50 base (A0/A1/A2) | 0x50 base (A0/A1/A2) | 0x50 base (A0/A1/A2) |
| Package | SOP-8 | SOIC-8 / TSSOP-8 | SOIC-8 / TSSOP-8 |
| Pinout | Identical 8-pin layout — 1:1 drop-in | ||
The comparison in one paragraph: all three are the same 24C128 protocol and the same pinout, so the swap is a BOM change, not a board change.
The M24128 pulls ahead on 4M-cycle endurance and guaranteed 1MHz at 3.3V. The AT24C128 wins on the widest supply range and lowest cost. The CAT24C128 matches the M24128's ECC at a 1M endurance rating. Which one lands on your BOM?
Clock speed vs supply — the derating that breaks 3.3V swaps: the M24128 and CAT24C128 hold 1MHz across the whole supply range. The AT24C128 only reaches 1MHz at 5V — at 2.7V–3.3V it falls to 400kHz.
A board configured for Fast-mode Plus at 3.3V must re-tune the bus after swapping to the Microchip part.
Choose the Microchip part for cost-sensitive designs and 1.7V rails. The AT24C128C runs down to 1.7V — the only candidate that survives a nearly-dead battery — and it's the most widely stocked 24C128 in the industry.
The trade: at 3.3V the bus tops out at 400kHz, and endurance is a quarter of the M24128's.
Choose the onsemi part for second-source security with ECC. It's the closest clone of the M24128 — same Fast-Plus 1MHz support, same on-chip ECC, same pinout — rated at 1M cycles instead of 4M. If the design already runs at 1MHz and wants a second supplier, this is the drop-in.
Step away from the 24C128 family when the data outgrows 16KB or the writes get extreme.
128Kbit is a parameter store, not a file system. For firmware, logs, or multi-MB assets, a SPI NOR flash (W25Q32-class) is the right bus. For near-unlimited endurance, FRAM exists — at several times the per-bit cost.
Shared 8-pin layout: all three parts use the identical pinout — A0/A1/A2, VSS, SDA, SCL, WC/WP, VCC. The swap needs no footprint change. Ground A0-A2 for address 0x50, and keep WC/WP tied low (or driven) — the one board mistake that makes every replacement appear dead.
Why does every swap story start with a silent write?
Layout rules that survive a swap: 4.7kΩ pull-ups on SDA/SCL, a 100nF decoupling cap across VCC and VSS close to the chip, and short bus traces. All three parts run the same protocol, so a board that worked with one works with the others.
| Model | Source | Why It Matters |
|---|---|---|
| M24C128 | ST same family | The M24128's 400kHz sibling — same company, same pinout, lower speed grade |
| FT24C128A | Fremont (Chinese) | Pin-compatible domestic 24C128 at the lowest cost tier; verify endurance before volume |
| 24C256 | Any 24C256 maker | Double the capacity on the same pinout and the same 2-byte addressing — the natural capacity upgrade |
| W25Q32JVSSIQ | Winbond SPI flash | Not pin-compatible, not I²C — the step-up when storage needs exceed EEPROM territory |
A: Yes — same pinout, same protocol, zero hardware change. The one firmware check: the AT24C128's clock speed is voltage-dependent. At 5V it runs 1MHz; at 2.7V–3.3V it drops to 400kHz. If your MCU configures 1MHz I²C at 3.3V, lower the bus speed after the swap.
A: The B-W suffix marks the Fast-mode Plus (1MHz) version. ST's M24C128 is the 400kHz grade; M24128-BW is the same die architecture bumped to 1MHz. Both are 128Kbit, both pin-compatible, so the suffix choice is a bus-speed decision.
A: Pin-compatible yes; datasheet-equal, verify first. FT24C128A-class parts work on the same footprint and protocol, but endurance and ECC aren't guaranteed equal to the branded parts. For volume boards we'd batch-test page-write wrap and address decode before committing.
A: The M24128 or the CAT24C128 — both hold 1MHz across their supply range. The AT24C128 only guarantees 1MHz at 5V. If the board runs 3.3V I²C at Fast-mode Plus, the CAT24C128 is the safe swap; the AT24C128 forces a 400kHz downgrade.
A: Yes — same pinout, same protocol, double the capacity. The 24C256 uses the same 2-byte internal addressing, so firmware that handles the M24128 works unchanged. The cost difference is small enough that many new designs just pick the 256.
A: Check the WC/WP pin first — it must be low for writes. The pin name differs (WC on ST, WP on Microchip/onsemi) but the behavior is identical: pulled high, the whole array is write-protected and every write is silently ignored. Second check: the device address — A0/A1/A2 must match the code's expectation.
A: When capacity needs more than 16KB, or when writes are both huge and frequent. Multi-MB data means SPI NOR flash (W25Q32-class). Near-unlimited small writes mean FRAM. The 24C128 family owns the middle: small, often-written, power-safe parameters.





