The CD74HC238E is a 3-to-8 line decoder/demultiplexer with active-HIGH outputs in DIP-16 — three address bits select one of eight outputs that goes HIGH while the rest stay LOW.
It's the mirror image of the 74HC138: identical pinout and logic, except the 138's outputs are active-LOW.
From what we see across Shenzhen logic-IC orders (2025–2026), the 238/138 pair is the go-to chip-select workhorse for 8-device buses — and the most common field failure is an enable pin left floating, not a bad chip.
One output at a time, HIGH when selected — that's the whole job.
DIP-16 pin functions: pins 1–3 are the address inputs A0–A2; pins 4–5 are active-LOW enables E1/E2 and pin 6 is active-HIGH E3; pins 7 and 9–15 are the eight active-HIGH outputs Y7–Y0; pin 8 is GND, pin 16 is VCC.
Note the gap between pin 7 and pin 9 — the Y7 output sits next to GND, so the output group reads Y7 on the left edge, Y6–Y0 across the right edge.
| Parameter | Value |
|---|---|
| Function | 3-to-8 line decoder / demultiplexer, active-HIGH outputs |
| Supply Voltage | 2V – 6V |
| Propagation Delay (A→Y) | ~14ns typ @ 5V, CL = 15pF |
| Input Capacitance | 3.5pF typ |
| Input Current | ≤1µA |
| Quiescent Supply Current | ~4µA max @ 25°C |
| Output Drive | HC family standard (4mA-class at 5V) |
| Operating Temperature | −40°C to +125°C |
| Logic Family | 74HC (CMOS levels); 74HCT variant accepts TTL levels |
| Package | DIP-16 (CD74HC238E); SO-16, TSSOP-16 variants exist |
Why do these numbers matter? The ~14ns address-to-output delay means a chip-select can decode in one logic step, and the 4µA quiescent current keeps the decoder invisible on the power budget — the 2–6V range covers 3.3V and 5V rails without level translation.
But how do the enables gate the outputs? All three must be satisfied before any output goes HIGH. E1 and E2 are active-LOW, E3 is active-HIGH: the decoder only operates when E1 = LOW, E2 = LOW, E3 = HIGH.
If any enable is in the wrong state, every output is forced LOW.
| E1 | E2 | E3 | Outputs Y0–Y7 |
|---|---|---|---|
| H | X | X | All LOW |
| X | H | X | All LOW |
| X | X | L | All LOW |
| L | L | H | Selected output HIGH per A0–A2 |
The double active-LOW plus single active-HIGH enable is the cascading feature — tie them in different patterns and you can stack decoders, or use one enable as a data input for demultiplexing.
Eight-device chip-select: three address lines from the MCU into A0–A2, the eight outputs into the enable pins of eight peripherals that need an active-HIGH select. One 238 replaces eight discrete address-decode gates, with the ~14ns delay sitting inside one bus cycle.
1-of-32 expansion: four 238s plus one inverter decode five address lines into 32 selects — the extra address bit picks which decoder is enabled through the enable inputs. The Arduino-forum example goes further: a 238 feeding the active-HIGH E3 enables of eight 138s gives 1-of-64 selection from six wires.
1-of-64 cascade: the 238's active-HIGH outputs feed the E3 enables of eight 138s; the same three address lines drive all decoder inputs. Six wires select one of 64 outputs — and only one output can be active at a time, which the enables enforce.
1. Floating enable pins — the top field failure. An E1 or E2 left unconnected floats into the wrong state and every output sits LOW.
The fix is boring and mandatory: tie unused enables to their active level (E1/E2 to GND, E3 to VCC) at layout time. Forum threads on "decoder does nothing" consistently resolve to this.
2. Confusing 238 and 138 output polarity. The two parts are pin-identical and the datasheet says so — only the outputs are non-inverting versus inverting. A board designed for the 138's active-LOW selects will have every LED, chip-enable, and load wired backwards with a 238.
An Arduino forum build hit exactly this: LEDs connected to ground the wrong way because the output polarity changed.
3. Assuming the outputs drive power loads. They're standard HC drive (4mA-class at 5V). A relay coil, buzzer, or LED directly at that current works; a MOSFET gate or a long wire at speed needs a buffer.
The decoder decodes; it doesn't drive power.
4. Forgetting the gap in the output numbering. Pin 7 is Y7 and pins 9–15 are Y6–Y0 — pin 8 is GND between them. Board layouts that route "outputs 0–7 in a row" across pin 7 to pin 9 silently mis-wire Y7.
5. Cascading with overlapping enables. When you stack decoders, only one output anywhere in the tree must be active. If two enable paths overlap, two loads get selected at once — the forum 1-of-64 build warns explicitly that the single-output-at-a-time rule is what the enable math is for.
A: Output polarity only — everything else is identical. The datasheet states it directly: the 238 is identical to the 138 but has non-inverting (active-HIGH) outputs. Same DIP-16 pinout, same address and enable logic, same speed. The 138's selected output goes LOW; the 238's goes HIGH. Pick by what your load expects.
A: One of the three enables is in the wrong state — usually floating. The decoder only operates with E1 = LOW, E2 = LOW, E3 = HIGH. Any other combination forces all outputs LOW. Tie E1 and E2 to GND, E3 to VCC, and drive them when you need strobe control — floating enables are the number one cause of "decoder does nothing."
A: Tie them to their active level — never leave them floating. Unused E1/E2 go to GND, unused E3 goes to VCC. CMOS inputs float into undefined states, and a floating enable makes the whole decoder behave randomly — it's a layout-time decision, not a field-time one.
A: Yes — cascade through the enables. Four 238s plus one inverter give 1-of-32 from five lines. The forum-tested pattern goes further: a 238's active-HIGH outputs drive the E3 enables of eight 138s for 1-of-64 from six wires. The enable structure is exactly what makes this expansion possible.
A: Output to LED to ground — because the selected output is HIGH. With the 238's active-HIGH outputs, the LED turns on when its output goes HIGH, so the LED sits between the output pin and GND through a current-limit resistor. With a 138 it's the mirror image (LED from VCC to the output). Getting this backwards is the classic polarity mistake between the two parts.
A: 2V to 6V — 3.3V and 5V rails both work directly. The HC family uses CMOS logic levels, so a 3.3V MCU can drive it without translation. If your system is mixed TTL/CMOS, the 74HCT variant accepts TTL input levels directly.
A: Yes — feed data into one enable input. With the address pins selecting the destination, drive an active-LOW enable (E1 or E2) with the data signal and keep the other enables active. The selected output echoes the data; the others stay LOW. Unused enables still need their fixed tie.
A: From ICMASS — DIP-16 or the SO/TSSOP variants on request. We stock the 238/138 decoder family with batch-verified part marking. For a decode tree, the same order can carry the 138s and the pull resistors — one shipment from Shenzhen covers the whole logic section.





