SN74HC138N — 3-to-8 Line Decoder/Demultiplexer with Active-Low Outputs (PDIP-16)

What Are the Technical Specifications of SN74HC138N?

Key numbers that matter: Per the TI SN74HC138 datasheet, the 15ns propagation delay is what makes it the standard memory decoder — the chip-select arrives quickly enough for 28MHz-class buses without wait states.

The three-enable scheme is the real feature: tie the enables to address bits or strobe lines, and one 138 gates memory, I/O, and peripherals from the same three decoded lines.

Active-low catches everyone once: the 138's outputs are inverted — the selected line goes low. CPU chip selects are almost always active-low, so the 138 matches the bus. If you want the opposite polarity, the 74HC238 is the active-high sibling.

When Should You Use (and NOT Use) the SN74HC138N?

✅ Use SN74HC138N when:

• Memory or peripheral chip select. Three address lines expand to eight chip-selects, and the 15ns delay keeps fast buses happy without wait states.
• Gating with your own control signals. The three enables double as data/strobe inputs — gate the decode with RD, WR, or an address strobe and you get a demultiplexer for free.
• Building a 4-to-16 or larger decoder. Two 138s cascade to 16 outputs; three reach 24 with no external inverters at all.
• 2V–6V mixed-rail systems. The same part runs 3.3V and 5V logic, and the 8µA quiescent current barely registers on the power budget.
• Through-hole prototypes. The PDIP body is breadboard-friendly and the whole family is still in active production.

❌ Don't use SN74HC138N when:

• You need active-high outputs. The 138 only drives the selected line low — use the 74HC238 for active-high selects without adding inverters.
• You're routing analog signals. A decoder switches digital levels, not signals — the 74HC4052 analog multiplexer handles audio or sensor routing.
• You need to serialize data. The 138 has no shift capability — the 74HC595 shift register is the output-expansion part.
• More than 8 selects with full enable flexibility. At that point the 74HC154 (4-to-16, single chip) usually beats two 138s on layout.

What Are the Alternatives to SN74HC138N?

Pick by polarity, then by scale. Active-low selects — the 138. Active-high — the 238. Two independent small decodes — the 139. A full 16-line map in one chip — the 154.

And if you're debating between a decoder and a shift register: the 138 answers "which one," the 595 answers "all of these."

What Are the Typical Applications of SN74HC138N?

Memory Map Decoding in a Retro-Style 8-Bit System: The 138 takes the upper address lines and produces chip-selects for RAM, ROM, and two I/O blocks. The 15ns delay keeps the selects valid before the CPU samples data — no wait states, no glue logic beyond the 138 itself.

Three-Enable Demultiplexer: With G1 and G2A tied to strobes, the 138 routes serial data to one of eight outputs. The enables become the data line — the datasheet's "enables can serve as data inputs" trick in practice.

Expanded 4-to-16 Peripheral Select: Two 138s plus one inverter select 16 peripherals from four address bits. The first chip covers addresses 0–7, the second covers 8–15, and both share the same three low address lines.

Why one inverter does it: U1's G1 gets the inverted A3, so it decodes when A3 is low; U2's G1 gets A3 directly, so it takes over when A3 goes high. Each chip holds its own 8 outputs idle-high — no conflict, no overlap, 16 selects from one extra inverter.

Why Buy SN74HC138N from ICMASS?

Genuine TI die, tested for the enable trap. We verify all three enables and the active-low output polarity on every incoming lot — a remarked 74LS138 or a mis-marked 238 would fail the check instantly, and those are exactly the parts that cost a week of debugging.

Logic family in one shipment. You're ordering the 138 for decode, the 595 for output expansion, and the 4052 for analog routing — we stock the ON and TI logic families from Shenzhen with same-day dispatch.

Cross-reference support. Not sure whether your board needs active-low (138), active-high (238), or a dual 2-to-4 (139)? Tell us the select polarity and the bus speed — we'll confirm the right part before you commit the BOM.

Frequently Asked Questions About SN74HC138N

Q1: What is the SN74HC138N?

A: A 3-to-8 line decoder/demultiplexer — three address bits select one of eight active-low outputs. Texas Instruments' SN74HC138N in PDIP-16 runs from 2V to 6V, with three enable inputs (G1 high, G2A/G2B low) and a 15ns typical propagation delay.

Q2: Are the 74HC138 outputs active-high or active-low?

A: Active-low — the selected output goes low, the other seven stay high. This is the number one surprise for new users, and it matches CPU chip-select conventions, which are almost always active-low. Want the opposite? The 74HC238 is the active-high version.

Q3: Why is my 74HC138 not decoding anything?

A: Check the three enables — G1 must be high, G2A and G2B must be low. On an 8085 forum thread the fix was exactly this: the user had G1 tied to GND and G2A/G2B tied to VCC — every enable backwards. The chip never decodes until all three agree.

Q4: What do G1, G2A and G2B do?

A: They gate the decode — all three must be in the right state for an output to fire. G1 is active-high; G2A and G2B are active-low. Beyond enabling, they can carry data or strobe signals, turning the 138 into a demultiplexer.

Q5: Can I cascade two 74HC138s into a 4-to-16 decoder?

A: Yes — one inverter is all it takes. Feed A0–A2 to both chips, run the fourth address bit to U2's G1 directly and to U1's G1 through an inverter. U1 decodes 0–7, U2 decodes 8–15, and there is no overlap.

Q6: Why do I see spikes or glitches on the outputs?

A: Internal race conditions when two address bits change at once — normal logic behavior, not a bad chip. A Stack Exchange answer points out that gates are undefined while inputs sit between thresholds; they settle right after the last input. Leave enough settling time before clock edges, or skew the inputs (the reason Gray-code counters exist).

Q7: Why do other decoder outputs go low during DRAM refresh?

A: The CPU's address bus is still active during refresh cycles — gate the decode with RD or WR strobes. Classic Z80 behavior: refresh addresses appear on the bus without valid strobes, and un-gated decoders respond to them. Adding the read/write signal to an enable pin fixes it.

Q8: My decoder only works when I touch the ground wire — why?

A: A poor ground connection, not a decoder problem. A Z80 builder on Stack Overflow had the same symptom — erratic decoding until touching the GND line. Re-check the ground path and the address-bus wiring before suspecting the chip.

Q9: How fast is the 74HC138?

A: 15ns typical propagation delay, about 28MHz maximum bandwidth. That covers memory decoding for most 8-bit and small 16-bit buses without wait states. Faster systems step up to the 74AHC138 class.

Q10: How much does SN74HC138N cost and is it in stock?

A: Volume pricing typically ranges from $0.05–$0.12/unit depending on quantity and date code. ICMASS stocks SN74HC138N in PDIP-16 and ships same-day from Shenzhen. Contact us for a quote on your specific quantity.