M24128-BWMN6TP.pdf
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M24128-BWMN6TP.pdf
The M24128-BWMN6TP is a 128Kbit (16K × 8) I²C serial EEPROM in SOP-8 from STMicroelectronics — running from 2.5V to 5.5V, clocking at 1MHz in Fast-mode Plus, with a 64-byte page write and a 5ms write cycle.
From what we see across Shenzhen lots (2025–2026), the M24128 is the default I²C EEPROM on parameter-storage footprints — calibration data, serial numbers, and factory settings that a SPI flash would chew through in a year of writes.
The most common field complaint isn't a dead chip — it's the WC pin left high silently rejecting every write, or the 2-byte internal address forgotten by firmware written for small 24C02-class parts.
| Parameter | Value |
|---|---|
| Type | Serial I²C EEPROM |
| Density | 128Kbit (16K × 8) |
| Package | SOP-8 (SOIC-8), ECOPACK2, MSL 1 |
| Supply Voltage (VCC) | 2.5V–5.5V |
| Clock Frequency | 1MHz (Fm+), 400kHz (Fm), 100kHz (Std) |
| Page Size | 64 bytes |
| Write Cycle Time (tWC) | 5ms max (byte and page write) |
| Write Endurance | >4 million write cycles |
| Data Retention | >200 years |
| Supply Current (ICC) | 2mA typ, 2.5mA max |
| Operating Temperature | −40°C to +85°C (industrial) |
| Device Address | 0x50 base (A0/A1/A2 selectable) |
| Read Modes | Random, sequential (auto-increment) |
| Protection | Hardware WC pin, ESD, ECC, power-on reset |
Key numbers that matter: the >4 million write cycles is the spec that separates EEPROM from flash — roughly 40× the endurance of a typical SPI NOR flash. That's the whole reason calibration data lives on an EEPROM. But why does endurance matter more than speed for a parameter store?
The 5ms write cycle is the hidden tax: after every page write the chip goes busy for up to 5ms. Poll for the ACK, don't just fire writes back-to-back.
✅ Use M24128-BWMN6TP when:
❌ Don't use M24128-BWMN6TP when:
| Model | Type | Key Difference | Best For |
|---|---|---|---|
| M24128-BWMN6TP | ST I²C EEPROM, SOP-8 | 128Kbit, 1MHz Fm+, 4M cycles, ECC | Parameter storage on I²C buses |
| AT24C128 | Microchip I²C EEPROM | Same 24C128 protocol, 400kHz typical | Second-source 24C128 footprints |
| CAT24C128 | onsemi I²C EEPROM | Same class, pin-compatible | Dual-source 24C128 designs |
| W25Q32JVSSIQ | Winbond SPI NOR flash | 32Mbit, 256-byte pages, ~100K cycles | Firmware, logs, large data storage |
| GD25Q16CTIGR | GigaDevice SPI NOR flash | 16Mbit SPI flash, low cost | Code storage and boot memory |
The 24C128 vs SPI flash decision in one line: EEPROM for data that changes often and must survive power cuts; SPI flash for data that's mostly written once and read many times. The 4M-cycle endurance gap is the deciding number.
SOP-8 pinout: pins 1–3 (A0/A1/A2) select the I²C address — all grounded gives 0x50. Pin 5 is SDA, pin 6 is SCL. Pin 7 (WC) is the write-control pin: tie it to GND for writes, high for hardware write protection.
I²C bus connection: SDA and SCL run from the MCU to pins 5 and 6, each with a 4.7kΩ pull-up to VCC — the pull-ups are mandatory, internal MCU pull-ups are not enough. A0/A1/A2 grounded selects address 0x50; WC to GND enables writes.
How do you know whether one chip can do both jobs?
Write endurance — EEPROM vs SPI NOR flash, this is why the chip exists:
Write a counter every second and the EEPROM lasts 46 days; the flash wears out the same section in just over a day. EEPROM is the only memory that makes frequent byte updates survivable.
Calibration and parameter storage: sensor offsets, gain coefficients, and trim values written at the factory and updated in the field. The 4M-cycle endurance absorbs firmware updates that rewrite the block a hundred times a day.
Serial numbers and device identity: one page holds the MAC address, serial, and manufacture date, written once and read at every boot. The 200-year retention means the identity outlives the product.
Configuration memory on shared I²C buses: alongside an RTC, a temperature sensor, and a battery monitor, the EEPROM rides the same two wires. The A0/A1/A2 pins let multiple EEPROMs coexist at different addresses.
Industrial and medical data logging: counters, event flags, and last-known-good state written on every power transition. EEPROM's atomic byte writes survive mid-write power loss without corrupting the neighboring data — something flash's block-erase can't promise.
Every lot tested for address decode and write behavior. We batch-verify the device responds at 0x50 and completes a full page write before shipping. Counterfeit and re-marked 24C128s commonly fail page-write wrap or read back garbage at the wrong address.
Cross-reference support for the 24C128 family. Not sure whether the board wants ST, Microchip, or onsemi? Send us your bus speed and capacity requirement — we'll tell you which part drops into the footprint.
BOM consolidation for control boards. The same product usually carries an MCU, an RTC, and the M24128. One shipment from Shenzhen covers the whole digital section.
Same-day dispatch, 5–10 days worldwide. Orders before 15:00 CST ship same day via DHL or FedEx. For volume orders, we source directly from the ST production line.
A: Run an I²C scanner and check the address pins — most "missing" EEPROMs are at a different address than the code expects. With A0/A1/A2 grounded the part answers at 0x50; any high pin shifts it (0x52, 0x54, etc.). Address pins must be tied to VCC or GND — floating inputs behave unpredictably. Missing 4.7k pull-ups cause the same symptom.
A: The WC pin is high, or the pull-up is missing. Tie pin 7 to GND to enable writes; tied high, the whole array is hardware-write-protected and every write is silently ignored. This is the first hardware check in every EEPROM troubleshooting thread.
A: The 128Kbit part needs a 2-byte internal address. Small EEPROMs like the 24C02 address within one byte; the 24C128/24C256 family sends two address bytes after the device address. Firmware that skips the second byte stalls on the first random-access operation.
A: 4.7kΩ on both SDA and SCL — the internal MCU pull-ups aren't enough. At 400kHz–1MHz the bus capacitance charges through the pull-ups; too weak and edges round off, too strong and the bus draws excess current. 4.7k is the standard starting point for 3.3V and 5V buses.
A: You're crossing the 64-byte page boundary in a single write. Page writes wrap within the page — bytes past the boundary land at the page start. Split writes that span pages into separate page-write operations; this is the classic 24C128 page-write bug reported on forums.
A: Up to 5ms — poll the ACK instead of delaying blindly. After a write the chip goes busy and won't ACK new start conditions. The robust pattern is ACK-polling: keep sending the device address until it ACKs, then continue. A fixed 5ms delay also works but wastes time on every write.
A: Yes — up to eight, by setting A0/A1/A2 differently on each. Give each part a unique address and the bus supports them all. On longer buses watch the total capacitance: roughly one device per 1m of wire at 400kHz, or drop the clock rate.
A: Yes — the M24128 runs from 2.5V to 5.5V, so power it at the MCU's rail. If the bus has 5V devices pulling up to 5V, put the EEPROM on the same 5V rail and level-shift the MCU side, or use series resistors. Don't pull a 3.3V-powered EEPROM's lines up to 5V.
A: For parameter storage, comfortably — do the math. A device rewriting 10 bytes every minute does 14,400 writes a day: 4M cycles lasts 277 days if hammering one address, but with wear leveling across 16KB it's effectively never worn out. Flash's 100K cycles would fail the same pattern in a week of concentrated writes.
A: Frequent small writes → EEPROM; big data or code → SPI flash. The EEPROM wins on endurance (4M vs 100K cycles), byte-granular writes with no erase step, and two-wire integration. The flash wins on capacity (32Mbit vs 128Kbit) and raw write throughput. See our EEPROM vs SPI Flash comparison for the full decision guide.
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| Part Number | M24128-BFMH6TG | M24128X-FCU6T/TF | M24128-BFMN6TP | M24128-BWMN6TP | M24128-BRMN6TP |
| Manufacturer | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Series | - | - | - | - | - |
| Package/Case | 5-UFDFN | 4-XFBGA, WLCSP | 8-SOIC (0.154", 3.90mm Width) | 8-SOIC (0.154", 3.90mm Width) | 8-SOIC (0.154", 3.90mm Width) |
| Packaging | Tape & Reel (TR) | Tape & Reel (TR) | Tape & Reel (TR) | Tape & Reel (TR) | Tape & Reel (TR) |
| Product Status | Active | Active | Active | Not For New Designs | Active |
| Programmable | Not Verified | Not Verified | Not Verified | Not Verified | Verified |
| Memory Type | Non-Volatile | Non-Volatile | Non-Volatile | Non-Volatile | Non-Volatile |
| Memory Format | EEPROM | EEPROM | EEPROM | EEPROM | EEPROM |
| Technology | EEPROM | EEPROM | EEPROM | EEPROM | EEPROM |
| Memory Size | 128Kbit | 128Kbit | 128Kbit | 128Kbit | 128Kbit |
| Memory Organization | 16K x 8 | 16K x 8 | 16K x 8 | 16K x 8 | 16K x 8 |
| Memory Interface | I2C | I2C | I2C | I2C | I2C |
| Clock Frequency | 1 MHz | 1 MHz | 1 MHz | 1 MHz | 1 MHz |
| Write Cycle Time - Word, Page | 5ms | 5ms | 5ms | 5ms | 5ms |
| Access Time | 450 ns | 650 ns | 450 ns | 450 ns | 450 ns |
| Voltage - Supply | 1.7V ~ 5.5V | 1.7V ~ 5.5V | 1.7V ~ 5.5V | 2.5V ~ 5.5V | 1.8V ~ 5.5V |
| Operating Temperature | -40°C ~ 85°C (TA) | -40°C ~ 85°C (TA) | -40°C ~ 85°C (TA) | -40°C ~ 85°C (TA) | -40°C ~ 85°C (TA) |
| Grade | - | - | - | - | - |
| Qualification | - | - | - | - | - |
| Mounting Type | Surface Mount | Surface Mount | Surface Mount | Surface Mount | Surface Mount |
| Supplier Device Package | 5-UFDFPN (1.7x1.4) | 4-WLCSP (0.83x0.83) | 8-SOIC | 8-SOIC | 8-SOIC |
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