STM32F103C8T6 Pinout (LQFP48)

Numbering convention: pin 1 sits at the top-left of the package (dot side), counting counter-clockwise: left side 1-12 top to bottom, bottom side 13-24 left to right, right side 25-36 bottom to top, top side 37-48 right to left.

Per the ST DS5319 datasheet: the three VDD/VSS pairs are all internally connected, but each needs its own decoupling capacitor placed at the pin.

FT marking in the datasheet means 5V-tolerant input — on this part that covers nearly all PA/PB GPIO, but not PC13-15, BOOT0, or the power pins.

Key Specifications

Key numbers that matter: the 72MHz core needs the HSE crystal + PLL — without an 8MHz crystal the chip runs on the 8MHz HSI oscillator, which works for blink tests and fails hard for USB timing and 72MHz performance.

The 20KB SRAM is the real constraint on this part, not flash — 64KB of code space fits more than most designs need, and 20KB of RAM fills fast with buffers and USB stacks.

Pin Functions That Actually Matter

Why do the small pin groups get most of this guide? Because they're where custom boards fail.

BOOT0 (pin 44) and PB2/BOOT1 (pin 20) — the boot-mode pair. Sampled at reset, they select the boot source: BOOT0=0 runs flash; BOOT0=1 with BOOT1=0 runs system memory (the factory UART bootloader); BOOT0=1 with BOOT1=1 runs SRAM.

On custom boards, BOOT0 needs a defined level — a 10k pull-down to GND with a jumper to 3.3V is the standard circuit.

VDDA (pin 9) — the pin that blocks programming. VDDA supplies the analog section and the GPIOA/SWD path on this family.

Per the ST community threads, a custom board with VDDA unconnected gives "no response from target" no matter what the debugger does. Bridge VDDA to VDD with 0Ω; add a ferrite bead plus 1µF and 100nF when ADC accuracy matters.

PA13 (pin 34) and PA14 (pin 37) — SWD. The two-wire debug interface needs no clock configuration to connect — but it dies if VDDA is missing or NRST floats.

Keep NRST pulled up (it has an internal pull-up; don't fight it) with a 100nF cap to ground.

PA9 (pin 30) and PA10 (pin 31) — USART1, the bootloader UART. The factory ROM bootloader speaks USART1 only. Adapter TX goes to PA10, adapter RX comes from PA9 — crossed the other way is the classic no-response cause.

Boot protocol per AN2606: 38400 baud, even parity, 8 data bits, echo disabled.

PA11 (pin 32) and PA12 (pin 33) — USB. The F103 has an internal 1.5kΩ D+ pull-up controlled by firmware (SOF-type connection). If firmware never enables it, the device won't enumerate — a software issue, not a missing resistor.

PD0 (pin 5) and PD1 (pin 6) — the 8MHz crystal. HSE runs through these pins with two ~20pF load caps to ground. A bad crystal or missing load caps is the classic "uploads fine, runs wrong" failure.

PC13 (pin 2) — the 3.3V-only trap. It drives the Blue Pill's LED, and it is not 5V-tolerant. Neither are PC14/15. Driving any of them from 5V logic is the fastest way to damage a board that "should be fine."

Typical Application Circuit (Blue-Pill Reference)

Common Mistakes When Using STM32F103C8T6

Here's the thing: every one of these failures shows up in forum threads weekly, and each traces back to one small pin group.

1. VDDA left unconnected — "No response from target". The #1 custom-board error. VDDA supplies GPIOA and the SWD unit; without it the debugger can't see the chip (mikrocontroller.net and SE threads document the exact symptom).

2. BOOT0 floating or wrong. On a custom board, a floating BOOT0 makes startup random. For flash run, BOOT0 must be low (10k to GND); for the UART bootloader, BOOT0 high then reset.

3. UART bootloader wiring crossed. The ROM bootloader is on USART1 (PA9 TX / PA10 RX). TX-to-TX wiring gives silence; so does using USART2/3, which the bootloader doesn't listen on. Boot protocol: 38400 baud, even parity, echo off (per AN2606).

4. 5V into a 3.3V-only pin. 2.0-3.6V on the supply; FT GPIO tolerate 5V logic — but PC13/14/15, BOOT0, and every power pin don't. A 5V signal into BOOT0 is the silent killer on custom boards.

5. NRST floating. Intermittent debugger connection and missed breakpoints trace back to a floating reset pin. It has an internal pull-up; add the 100nF cap to GND and route it to a header.

6. Bad or missing 8MHz crystal. Uploads succeed, then the code runs at wrong speed or not at all. Check the crystal, its load caps, and the soldering before suspecting the firmware.

7. Counterfeit F103s on cheap boards. Marking without an ST logo, wrong die reading, and ST Flash Loader failures are the pattern. For production, buy from an authorized line and verify the part marking (from what we see in Shenzhen, 2025–2026).

Frequently Asked Questions About STM32F103C8T6 Pinout

Q1: Can I power it with 5V?

A: No — the chip runs from 2.0-3.6V, typically 3.3V. The Blue Pill takes 5V at its USB/5V pins only because an onboard regulator drops it. What tolerates 5V is most of the GPIO (FT-marked), not the supply. A 5V rail into VDD is damage; a 5V logic signal into an FT pin is fine.

Q2: Which pins are 5V-tolerant?

A: Nearly all PA/PB GPIO carry the FT (5V-tolerant) mark in DS5319. The exceptions that bite: PC13/14/15 are 3.3V-only, BOOT0 is 3.3V-only, and the power/analog pins are supply. PA11/PA12 are FT-marked but still subject to USB electrical limits when used as USB.

Q3: How do I flash it over UART?

A: BOOT0 to 3.3V, reset, then talk to USART1 at 38400 baud, even parity, 8 data bits, echo off. Adapter TX → PA10, adapter RX ← PA9. After flashing, BOOT0 back to GND and reset to run from flash. The ROM bootloader only listens on USART1 — USART2/3 are ignored.

Q4: What do BOOT0 and BOOT1 actually select?

A: They pick the boot source, sampled once at reset. BOOT0=0 boots flash (normal run). BOOT0=1 with BOOT1=0 boots system memory (the factory UART bootloader). BOOT0=1 with BOOT1=1 boots SRAM (for RAM debugging). PB2 doubles as BOOT1 but works as normal GPIO after boot.

Q5: Does it need the 8MHz crystal?

A: For blinking, no — the internal 8MHz HSI runs it. For 72MHz and USB, yes. The PLL needs HSE to reach 72MHz with calibrated accuracy, and USB timing depends on a precise 48MHz clock. RTC needs the separate 32.768kHz LSE crystal on PC14/PC15. Projects that "work on the bench" and fail in the field are usually missing one of these.

Q6: Why does my custom board give "no response from target"?

A: Check VDDA first, then NRST, then the SWD pins. VDDA unconnected starves GPIOA and the SWD unit — the documented #1 cause (SE and mikrocontroller.net threads). NRST floating causes intermittent drops. Then confirm PA13/PA14 aren't reassigned by leftover firmware.

Q7: How do I spot a counterfeit STM32F103C8T6?

A: Check marking, die reading, and bootloader behavior. Genuine parts carry clean ST marking and read a real ID. Clones often fail ST's Flash Loader with a "chip protection" style error, show wrong or erasable ID, and behave differently at the bootloader UART. From what we see in Shenzhen (2025–2026), remarked F103s concentrate in "too cheap" lots — verify the lot before volume.