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SPI Flash Selection Guide — How to Choose the Right NOR Flash for Your Embedded Design

2026/6/26 17:24:07

SPI Flash Selection Guide — How to Choose the Right NOR Flash for Your Embedded Design

Choosing SPI NOR Flash comes down to four questions: how much firmware space do you need, does your design require OTA updates, what voltage does your system run at, and what is your budget per unit for external memory.

The W25Q64 (64Mbit / 8MB) is the most popular choice across embedded designs because it hits the sweet spot between cost and capacity. But depending on your application, a smaller or larger chip may be the right call.

How Much Flash Capacity Do You Actually Need?

This is the most common question, and the answer depends on three usage scenarios.

Firmware-only storage. If the Flash holds one firmware image and nothing else, measure your compiled binary. A simple IoT sensor firmware is typically 200KB–500KB. A full RTOS-based application with TCP/IP stack and USB stack runs 1MB–2MB. For this use case, a 16Mbit (2MB) or 32Mbit (4MB) chip is sufficient.

Firmware + OTA update staging. If the device downloads firmware updates over the air, the Flash must hold the active image plus the downloaded staging image simultaneously. This doubles the firmware space requirement. A 2MB firmware needs 4MB for active + staging. The W25Q32 (4MB) is the minimum viable choice. The W25Q64 (8MB) provides comfortable headroom.

Firmware + OTA + filesystem + assets. Add a recovery image, configuration filesystem, GUI assets, or data logging, and the requirements grow quickly. A typical WiFi camera with web interface may need 2MB firmware + 2MB staging + 1MB filesystem + 1MB UI assets = 6MB. This pushes you into the 64Mbit or 128Mbit range.

Capacity Checklist

ApplicationRecommended SizeWhy
Simple sensor, no OTA16Mbit – 32MbitFirmware under 1MB, minimal config
IoT product with OTA32Mbit – 64MbitActive + staging + config
GUI / display product64Mbit – 128MbitFonts and assets are large
Linux boot + rootfs128Mbit+Kernel and filesystem need space

What Clock Speed and Interface Do You Need?

All modern SPI Flash chips support standard SPI, Dual SPI, and Quad I/O modes. The practical question is whether you need the extra throughput from Quad I/O.

Standard SPI (single I/O) at 40–80MHz provides 5–10 Mbytes/s read throughput. This is sufficient for loading firmware into RAM at boot time, where a 2MB image loads in under 0.4 seconds at 10MB/s.

Quad I/O SPI at 80–133MHz provides 40–66 Mbytes/s read throughput. This is necessary for execute-in-place (XIP) operation, where the CPU fetches instructions directly from the Flash.

InterfaceMax ThroughputWhen It Matters
Standard SPI5 – 10 MB/sBoot loading, configuration storage
Dual SPI10 – 20 MB/sFirmware updates, moderate read traffic
Quad I/O40 – 66 MB/sXIP code execution, display framebuffer

Recommendation: If your MCU has a QSPI controller with memory-mapped mode, use Quad I/O even if you do not plan XIP now — the overhead for enabling it in firmware is minimal, and it provides bandwidth headroom.

3.3V or 1.8V — Which Supply Voltage Matches Your System?

3.3V Flash (2.7V – 3.6V) is the standard. The Winbond W25Q32JV and W25Q64JV series, Macronix MX25L series, and Gigadevice GD25Q series all operate at 3.3V. This matches the I/O voltage of most MCUs (STM32, ESP32, NXP i.MX RT).

1.8V Flash (1.65V – 1.95V) is used in low-power and battery-operated designs. Winbond offers the W25Q32FW and W25Q64FW series for 1.8V operation. Same command set, different voltage range.

A common mistake: Wiring a 3.3V Flash to a 5V MCU without level shifters. The absolute maximum input voltage for 3.3V SPI Flash is approximately 4.0–4.6V. A 5V logic signal will damage the chip.

What About Endurance and Data Retention?

The datasheet specification of 100,000 erase/program cycles per sector and 20-year data retention applies to both the W25Q32 and W25Q64.

Endurance in practice: 100K cycles per sector means a data logging application writing 4KB every minute would exhaust one sector in approximately 69 days. With 1024 sectors (W25Q32) and wear leveling, the total writes before any sector fails are approximately 100 million sector-writes.

Data retention in practice: 20-year retention is guaranteed at 25°C with 100K cycles written. At higher temperatures, retention decreases — at 85°C, typical retention is approximately 5 years for a fully cycled chip. For a chip with 10K cycles, retention at 85°C is approximately 20 years.

If your application runs at high temperatures (automotive under-hood, industrial ovens) or requires high-frequency logging, consider SLC NAND or an FRAM device instead.

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