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Q: How do I wire the enables so the chip actually decodes?

G1 to VCC, G2A and G2B to GND - all three, explicitly. The decoder runs only when G1 is HIGH and both G2 inputs are LOW. Leaving any enable floating is the most common chip-does-nothing cause; tie all three to rails and the outputs start answering the address lines.

Q: My selected output goes LOW - is the chip broken?

No - active-low is the design. The 74HC138 pulls the selected Y output low and holds the other seven high, which is exactly what chip-select nets want. If your load needs the selected line to go HIGH, use the 74HC238 - same pinout and function, non-inverting outputs.

Q: Can I cascade two chips into a 4-to-16 decoder?

Yes - that's what the third enable is for. Feed A, B, C to both chips in parallel and drive the fourth address bit into one chip's G1 (active-high) and into the other chip's enable through an inverter. A 5-line-to-32-line decoder takes four 138s plus a single inverter.

Q: How do I spot a counterfeit SN74HC138N?

Check the marking, the package, and the quiescent current. Genuine TI parts read SN74HC138N with clean laser marking on a true 19.3mm PDIP body. ICC should sit near 8µA typ at 6V with inputs tied - a remarked or die-short part draws orders of magnitude more.

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SN74HC138N Pinout, Pin Functions & Common Mistakes — 3-to-8 Line Decoder

2026/9/4 13:11:27

The SN74HC138N is TI's 74HC138 3-to-8 line decoder in the 16-pin PDIP (N) package — three select inputs choose one of eight active-low outputs, enabled by a three-input enable block. It runs from 2V to 6V and switches with a typical 15ns propagation delay.

Per the TI datasheet (SCLS107G, rev G), the chip exists for memory chip-select decoding and data routing, and it shows up in the datasheet's own application list: LED displays, servers, white goods, and building or factory automation.

From what we see across Shenzhen lots (2025–2026), the 74HC138 still ships in volume into appliance control panels and PLC I/O boards as a 3-line-to-8-way selector — cheap IO expansion and active-low chip-select generation.

The pin that kills the design isn't on the output side. It's the enable trio: G1 must be HIGH while G2A and G2B are both LOW — and floating enable pins behave like neither. That one fact explains most "chip does nothing" forum threads.

SN74HC138N Pinout (DIP-16)

Pin	Name	Type	Description
1	A	Select input	Address bit A, least significant (LSB)
2	B	Select input	Address bit B
3	C	Select input	Address bit C, most significant (MSB)
4	G2A	Enable, active-low	Must be LOW for the decoder to run
5	G2B	Enable, active-low	Must be LOW for the decoder to run
6	G1	Enable, active-high	Must be HIGH for the decoder to run
7	Y7	Output, active-low	Selected when C B A = 111
8	GND	Power	Ground
9	Y6	Output, active-low	Selected when C B A = 110
10	Y5	Output, active-low	Selected when C B A = 101
11	Y4	Output, active-low	Selected when C B A = 100
12	Y3	Output, active-low	Selected when C B A = 011
13	Y2	Output, active-low	Selected when C B A = 010
14	Y1	Output, active-low	Selected when C B A = 001
15	Y0	Output, active-low	Selected when C B A = 000
16	VCC	Power	2V to 6V supply

Two things the pin table hides. First, the outputs are numbered from the wrong end: Y7 sits next to the address inputs (pin 7) and Y0 sits at the bottom (pin 15) — the physical order is the mirror of the logical order.

Second, every Y output is active-low: the selected one goes LOW and the other seven stay HIGH.

Key Specifications

Parameter	Value
Function	3-line to 8-line decoder / demultiplexer, inverting outputs
Package	SN74HC138N: PDIP-16 (19.32mm × 6.35mm); family also in SOIC/SSOP/TSSOP
Supply Voltage (V_CC)	2V to 6V
Quiescent Current (I_CC)	80µA max, 8µA typ at 6V
Propagation Delay (t_pd)	15ns typ
Output Drive	±4mA at 5V; drives up to 10 LSTTL loads
High-Level Input Voltage (V_IH)	3.15V min at V_CC = 4.5V (70% of V_CC)
Low-Level Input Voltage (V_IL)	1.35V max at V_CC = 4.5V (30% of V_CC)
Input Capacitance (C_i)	3 to 10pF
Input Transition Rise/Fall	500ns max at V_CC = 4.5V
Outputs	8, active-low; ±25mA absolute max continuous per output
Thermal (PDIP N)	R_θJA 54.8°C/W
Temperature Range	-40°C to +85°C
Enable logic	G1 = HIGH and G2A = G2B = LOW to decode; else all Y HIGH
Datasheet	TI SCLS107G (Rev G, Oct 2021)

Key numbers that matter: the input thresholds are CMOS-ratioed — 70% of V_CC for a logic high, 30% for a logic low. The 80µA max quiescent current is the other number that matters on battery boards.

Why does the 70% rule matter? It decides whether your MCU can drive the chip at all — a 3.3V logic rail works when the chip runs at 3.3V and gets marginal when the chip runs at 5V.

How the Decoding Actually Works

C B A (binary)	Selected Output
000	Y0 goes LOW, Y1-Y7 stay HIGH
001	Y1 goes LOW, others HIGH
010	Y2 goes LOW, others HIGH
...	...
111	Y7 goes LOW, others HIGH

The enable rule gates all of it: the chip only decodes when G1 = HIGH, G2A = LOW, and G2B = LOW. If any of the three is wrong — including floating — every output stays HIGH and the chip looks dead.

But why do two active-low G2 inputs exist? Because cascading and strobing both need a second gate signal you can drive independently.

One more thing: A is the least significant bit and C is the most significant. Wire your microcontroller lines in that order, or your "output 3" turns out to be output 6.

Pin Functions That Actually Matter

The enable trio (G1, G2A, G2B): The active-high G1 plus the two active-low G2 inputs form an AND gate in front of the decoder. G2A and G2B are effectively OR'd — if either one is HIGH, the chip is disabled.

That structure is what makes cascading free: one chip's G1 can be driven directly by a fourth address bit.

The active-low outputs: Each Y output sinks current when selected. That matches chip-select nets (memory /CS, peripheral /CE) and LED cathodes perfectly, and it is why a novice expecting a HIGH output thinks the chip is broken. Need active-high selects? That's the 74HC238 — same pinout, opposite polarity.

The address inputs: A, B, C are pure CMOS inputs with no pull-ups or pull-downs. TI's own guidance (application note SCBA004) is blunt: unused inputs must be tied to V_CC or GND. A floating CMOS input drifts, and a drifting select input decodes randomly.

Typical Application Circuit — 3 MCU Lines to 8 Selects

Three GPIO lines become eight chip selects: the MCU drives A, B, and C; G1 ties to V_CC and both G2 inputs tie to GND so the decoder always runs. Outputs Y0-Y7 are active-low, ready for memory or peripheral enable pins.

To turn the decoder into a strobe instead of a static select, drive one G2 input from the MCU — the outputs then only assert while that line is low. The other enable inputs stay tied to their active states.

What the 16 pins actually do:

Active-low outputs (Y0-Y7)8 pins

Select inputs (A, B, C)3 pins

Enable inputs (G1, G2A, G2B)3 pins

Power (VCC, GND)2 pins

Eight of the sixteen pins are outputs — the decoder is an address-to-IO expander at heart, and the three enables are where the design mistakes live.

Common Mistakes When Using SN74HC138N

Floating enable pins. All About Circuits thread 97523 asks the question directly: "if G2A isn't connected, isn't it already logically low?" No — a CMOS input floats, and the chip behaves erratically or stays disabled. Tie G1 to V_CC and G2A/G2B to GND explicitly.

Getting one of the three enables wrong. The enable block is an AND of G1-high and both-G2-low; if either G2 input is high, the whole chip is off. The G2 inputs are OR'd together — check both, not one.

Expecting the selected output to go HIGH. The 138's outputs are active-low by design. StackExchange question 635026 is a whole thread about a function table that looked "wrong" for this reason. If your load needs active-high, the pin-compatible 74HC238 is the part.

Driving a 5V-powered HC from 3.3V logic without checking thresholds. At V_CC = 5V the high threshold is about 3.5V (70% of rail) — a 3.3V MCU output sits in the forbidden zone.

Run the chip at 3.3V too, or switch to the 74HCT138, whose TTL-compatible thresholds accept 5V and 3.3V logic alike.

Reversing A, B, and C against the MCU port. A is LSB, C is MSB. Wire PB0→A, PB1→B, PB2→C — the classic bug is wiring them in physical port order and watching outputs come out scrambled.

Driving LEDs or relays without a resistor or buffer. Outputs are rated ±4mA at 5V and 25mA absolute max. An LED needs its series resistor; a relay coil needs a transistor — the 138 is a decoder, not a driver.

Frequently Asked Questions About SN74HC138N Pinout

Q1: How do I wire the enables so the chip actually decodes?

A: G1 to V_CC, G2A and G2B to GND — all three, explicitly. The decoder runs only when G1 is HIGH and both G2 inputs are LOW. Leaving any enable floating is the most common "chip does nothing" cause in the forums (AAC 97523); tie all three to rails and the outputs start answering the address lines.

Q2: My selected output goes LOW — is the chip broken?

A: No — active-low is the design. The 74HC138 pulls the selected Y output low and holds the other seven high, which is exactly what chip-select nets want. If your load needs the selected line to go HIGH, use the 74HC238 — same pinout and function, non-inverting outputs.

Q3: 74HC138, 74HCT138, or 74LS138 — which do I need?

A: HC for CMOS logic at 2-6V, HCT for mixed TTL-level inputs, LS only for legacy 5V TTL boards. HC input thresholds sit at 70% of V_CC, so a 3.3V MCU needs the chip powered at 3.3V too. HCT uses TTL thresholds (about 0.8V and 2.0V), so it accepts 3.3V and 5V logic while running at 5V. LS is the 1980s original — slower, hungrier, and only at 5V.

Q4: Can I cascade two chips into a 4-to-16 decoder?

A: Yes — that's what the third enable is for. Feed A, B, C to both chips in parallel and drive the fourth address bit into one chip's G1 (active-high) and into the other chip's enable through an inverter. NXP's datasheet notes that a 5-line-to-32-line decoder takes four 138s plus a single inverter.

Q5: Can it drive LEDs or relays directly?

A: LEDs yes with a series resistor; relays no — use a transistor. Each output is rated for 4mA at 5V and 25mA absolute maximum. A typical LED with a 330Ω-1kΩ resistor on the active-low output works; a relay coil needs a driver transistor, because the 138 is a decoder, not a power driver.

Q6: All outputs stay HIGH no matter what I do — what do I check first?

A: Check the three enables with a meter, then the supply, then the address wiring. Measure G1 at V_CC and G2A/G2B at GND — the 51hei running-light threads trace exactly this failure to an unwired enable. Then confirm the chip has a regulated supply (a weak battery rail reads "5V" with no load and collapses under the chip) and that A, B, C are in LSB-to-MSB order.

Q7: What are the outputs when the chip is disabled?

A: All eight sit HIGH — that's the inactive state, not a fault. When any enable is wrong, every Y output releases high. For memory decoding this is the safe default: no chip-select is ever wrongly asserted. If you see one output low when the chip should be off, suspect an address or enable short, not the decoder logic.

Q8: How do I spot a counterfeit SN74HC138N?

A: Check the marking, the package, and the quiescent current. Genuine TI parts read SN74HC138N with clean laser marking on a true 19.3mm PDIP body. The fast check is electrical: I_CC should sit near 8µA typ at 6V with inputs tied — a remarked or die-short part draws orders of magnitude more. From what we see in Shenzhen (2025–2026), this class of logic chip is re-marked less than power parts, but the ICC test catches the bad lots.