NCE40H29D Pin Diagram and Pin Functions

Pin 1 gate, pin 2 drain, pin 3 source — read straight off the schematic figure on page 1 of the V2.0 datasheet, which labels them 1, 2 and 3.

On the package drawing the same three numbers sit on the three leads, and the tab carries the drain marking. Nothing about the numbering is package-specific: it is the same on the TO-252 and TO-220 rungs of this family.

Key Specifications

Two rows that matter for layout are missing from this sheet. There is no internal gate resistance figure, and no junction-to-ambient thermal figure — the two numbers a board designer would reach for first.

The gate charge and capacitances are all specified at I_D = 20A, well below the 290A headline rating, so treat them as small-signal values rather than working-condition ones.

Typical Application Circuit

The gate resistor goes at the pin, not at the driver. Placing it close to the gate separates the trace inductance from the device's input capacitance, which is the difference between a damped edge and a ringing one.

With 10331pF of input capacitance and 239nC of gate charge, this part presents a heavier load than anything else on its ladder, so the gate loop has more to ring with.

The drain connection carries the tab node as well as the lead, which is why the copper under the tab is part of the circuit and not just a mounting surface.

The body diode is drawn with its anode at the source node and its cathode at the drain, which is the direction it conducts in an N-channel device when the source is pulled above the drain.

Common Mistakes When Using NCE40H29D

1. Treating the tab as a mounting point rather than the drain

The tab is pin 2 and it is live at the drain potential. One documented case on a D2PAK layout ran the package's thermal pad to ground, routed pads labelled as heatsinks to the gate net, and dropped a via array through the gate area into the ground plane.

The result was a set of wrong and shorted connections that only showed up as unexplained heating. Confirm the tab's net against the datasheet before the board is fabricated — on this part that node is also the 0.48°C/W thermal exit.

2. A tab pad cut exactly to the outline

The pad should be at least as large as the exposed tab and extend past it. Power dissipation in this package is a function of the drain pad area, so a minimum-size pad is a minimum-power design.

Published DPAK-family thermal data shows the junction-to-ambient figure falling steeply with copper area up to roughly 6cm² before it flattens.

3. Copper under the tab with no via field

Copper without vias keeps the heat in the surface layer. The usual arrangement is a grid of small vias across the tab into an inner plane — around 0.3mm holes on a 1.0–1.2mm pitch.

Those vias often double as the electrical connection for the drain node, which is another reason not to route the load return through them.

4. A one-to-one stencil opening on the tab

The tab opening is normally reduced to about half the pad area, while the lead openings stay one-to-one. A full-size opening deposits too much solder, which causes misalignment and tombstoning on a package this heavy.

The same rule applies to the gap between the tab pad and the lead pads: keep it free of copper and mask so solder cannot bridge across it.

5. Driving the gate from a rail below 10V

This sheet publishes no 4.5V resistance row. Every other part on its ladder prints one; this one does not, which makes it a standard-level device. The only resistance figure guaranteed here is 2.4mΩ maximum at 10V.

Below the lowest rated gate voltage the device operates in the linear region rather than as a switch, where cell current sharing is poor and the temperature coefficient can turn negative.

6. Assuming a known internal gate resistance

This sheet does not publish one. Its 30V sibling prints 1.6Ω, so the figure exists in the family — it just is not on this datasheet.

That leaves the external gate resistor doing all the damping, and it makes bench measurement the only way to know what the loop actually looks like on your board.

Where to Buy NCE40H29D

We stock this part with the official PDF on hand and sample the one resistance row the sheet publishes — 2.4mΩ maximum at 10V, measured at 20A.

We also check gate charge, because 239nC is the heaviest gate load on this ladder and a remarked die with a lighter gate will show up there before it shows up anywhere else.

Orders ship same day from Shenzhen, and we will say plainly when a smaller package is the better answer for your layout.

Frequently Asked Questions

Q1: Which pin is the drain on a TO-263?

A: Pin 2, and the tab is the same node. The drain reaches the board twice on this package — once through the centre lead and once through the soldered tab. Both are electrically identical.

Q2: Why does the drain come out on the tab at all?

A: Because the die is mounted on the lead frame with its drain side down. For a vertical power MOSFET the substrate is the drain, so the shortest thermal path out of the silicon is also the drain terminal. The package's cooling and its pinout are the same decision.

Q3: What happens if I connect the tab pad to ground?

A: You short the drain to ground through a very low-resistance path. The tab is not isolated. A documented D2PAK case with the thermal pad routed to ground produced wrong and shorted connections that surfaced as unexplained heating rather than as an obvious failure.

Q4: Do I need a gate resistor?

A: Yes, and it belongs at the gate pin. Without series resistance the gate loop — trace inductance plus input capacitance — is underdamped and rings on every edge. Published bench work stepped a gate resistor from 0Ω to 10Ω and found the ringing stopped at 10Ω.

Q5: How much copper does the tab need?

A: More than the tab outline, and with vias. The datasheet gives 0.48°C/W junction-to-case but no board figure at all, so there is no number here to design against. Published DPAK data shows the ambient figure improving steeply to about 6cm² of copper.

Q6: Is the source lead shared between the load and the gate?

A: Yes. Pin 3 carries both the load return current and the gate return current. That shared segment is why the gate drive sees a voltage proportional to the load current's rate of change, and why a Kelvin connection is not available in this package.

Q7: Can I drive this from a microcontroller pin?

A: Not directly. The gate charge is 239nC and there is no 4.5V resistance row, so this is a 10V-drive part with the heaviest gate on its ladder. It needs a driver stage, not a port pin and a resistor.

Q8: What should I check first on a new board?

A: Continuity between pin 2 and the tab, before power is applied. That single measurement confirms the drain net is the one you intended, which is the mistake that damages boards rather than parts.