NCE30H15K Pin Diagram and Pin Functions

Key Specifications

The sheet runs to 21 rows of electrical data at v1.0. These are the ones that decide a layout or a driver:

What does the driver actually see when it looks into pin 1? Not a single capacitance, and not a resistor either. It sees a charge of 38nC split across three phases, and one of them is the phase where the drain moves.

The last two rows are the ones the gate loop acts on. During the plateau the drain is slewing, so the loop inductance and the Miller charge fight each other — and whatever they do shows up as ringing on pin 1.

Typical Application Circuit — and the Loop That Matters

A low-side switch on a 24V rail, drawn with the gate return as the feature rather than an afterthought:

Three details in that drawing carry the design. The gate resistor sits at the gate, not at the driver — a resistor at the driver leaves the trace between it and the gate as an undamped stub.

The return path reaches the source pin rather than a ground plane across the board. And the source is the one node shared by the load current and the gate current.

But why does a loop that carries only nano-coulombs matter on a 150A switch?

Because the loop is an inductor, and the gate is a capacitor. Together they ring at the switching edge, and the ring lands directly on V_GS. A gate that rings past the 1.2V minimum threshold turns a minimum-spec device partly on when it should be off.

Common Mistakes When Using the NCE30H15K

Every one of the 7 mistakes below comes from a forum thread rather than a datasheet — the sheet states the limits, the forums show what happens when a layout ignores them.

• Treating the tab as a ground connection. Generic DPAK layout advice often says to stitch the tab pad to the ground plane. On this part the tab is the drain, at full rail plus overshoot. Bolt a chassis or heatsink to that copper and you have tied your switching node to earth.
• Routing the gate return through a distant ground plane. One documented bench case ran the gate return under the MOSFET and back through 8mm of trace — roughly 15nH against about 3nF of input capacitance. Moving the driver ground to share copper with the FET source cut the loop to about 2nH and the measured ringing from 30V to 4V, with no component changes.
• Putting the gate resistor at the driver. Forums list this repeatedly as a layout defect: the damping element has to sit at the gate pin, or the trace between resistor and gate rings undamped.
• Adding capacitance to the gate to stop ringing. A capacitor across gate and source does not damp the resonance — it changes its frequency, and it adds load to the driver. Damping is a series resistor's job.
• Printing solder paste over the thermal vias in the tab pad. An EDABoard thread documents twelve vias under a DPAK drain pad producing solder shards out of the via bottoms after reflow, piercing a thermal pad and shorting to an earthed heatsink. The fixes are a reduced paste aperture over the tab or plugged vias in production.
• A full-pad stencil opening over the tab. Trapped flux gas under a large pad produces voids, and past about 25% voiding the thermal resistance rises. A window-pane stencil pattern or a split tab pad is the standard mitigation.
• Running the driver a long way from the gate. Twenty nanohenries is about 2cm of PCB trace. Bench wiring measured in centimetres, rather than millimetres, is where most of the "it worked on the bench but not in the product" stories come from.

Frequently Asked Questions

Q1: Which pins are which on the NCE30H15K?

A: Pin 1 is the gate, pin 2 is the drain, pin 3 is the source, and the tab is the drain. The tab and pin 2 are the same net internally. Looking at the top of the package with the leads toward you, that is gate on the left, drain in the middle, source on the right.

Q2: Can I connect the tab to my ground plane to help it cool?

A: No — the tab is the drain. On this package the thermal pad is electrically live at the switching node. Solder it to a dedicated copper island with thermal vias into an inner layer, sized for heat rather than for a ground connection. Tie it to ground and the supply is shorted through the die.

Q3: How close does the gate driver need to be?

A: As close as the layout allows, and closer than feels necessary. Loop inductance scales with area, and roughly 20nH corresponds to about 2cm of trace. Forum threads regularly describe several centimetres of gate wiring as a cause of ringing and destruction. Distance measured in millimetres is the target.

Q4: Should the gate resistor go at the driver or at the gate?

A: At the gate pin. A resistor at the driver leaves the trace from resistor to gate as an undamped stub that still rings. Every layout critique in the forum record lists a gate damping resistor placed away from the gate as a defect.

Q5: What is the Miller plateau, and why does this part care?

A: It is the part of the turn-on where the gate voltage stalls while the drain slews. On this device it accounts for 13nC of the 38nC total, and it is the phase where loop inductance and drain dv/dt interact most directly. A flat plateau with a clean edge means the loop is behaving.

Q6: Does it help to add a capacitor from gate to source?

A: No — it changes the ringing frequency rather than damping it. Gate-source capacitance adds to the input capacitance and loads the driver without absorbing energy. The damping element is a resistor in series with the gate; for asymmetric edges, a diode across that resistor is the usual refinement.

Q7: Can I put vias in the tab pad?

A: Yes, and they are normal practice — with three conditions. Give them no thermal reliefs, do not print paste directly over them, and plug them for production boards where the underside needs to stay clean. Tenting the top while leaving the bottom open is the usual compromise for prototypes.

Q8: How much gate current does 38nC actually require?

A: Charge divided by switching time. Driving 38nC in 100ns needs about 380mA of average gate current, and the peak is higher through the plateau. That is why the driver's output trace wants to be short and wide rather than a thin signal line.