The NCE0203S is a 200V/3.9A N-channel trench MOSFET in SOP-8 with pins 1–3 as source, pin 4 as gate, and pins 5–8 as drain — the standard NCE SOP-8 order, per the v1.1 pin diagram.
It is a 10V-gate part with a 2–4V threshold, 79mΩ max at 10V, and a 3W budget in a no-pad package — which means most field failures around this part are not the silicon, they are the wiring and the layout around it.
The pin-1 dot and the beveled edge anchor the orientation: left column reads 1–2–3–4 top to bottom, right column reads 5–6–7–8 bottom to top.
| Pin | Name | Type | Notes |
|---|---|---|---|
| 1, 2, 3 | Source | Power | Common source node; carries the return current — pour copper and keep the gate return off this pour |
| 4 | Gate | Input | High-impedance input; 2–4V threshold, 10V drive required for guaranteed RDS(on) |
| 5, 6, 7, 8 | Drain | Power | Switched node; four pins share the drain — most of the heat exits through these |
Only three nets leave this part — but one of them is at up to 200V when the FET is off, and one of them is a floating high-impedance input. That combination is where almost every field failure around this chip starts.
| Parameter | Value |
|---|---|
| VDS / VGS | 200V / ±20V |
| ID (25°C) / @100°C | 3.9A / 2.8A |
| IDM pulsed | 30A |
| RDS(on) @ 10V | 79mΩ max (typ 56mΩ, ID = 3.7A) — 10V row only |
| VGS(th) | 2.0V min / 3.0V typ / 4.0V max |
| Qg / Qgs / Qgd | 38 / 9 / 15 nC (VGS = 10V) |
| Ciss / Coss / Crss | 4200 / 163 / 75 pF (measured at VDS = 25V) |
| Switching (td(on)/tr/td(off)/tf) | 15 / 13 / 26 / 14 ns (VDD = 100V, ID = 2.2A) |
| PD / RθJC | 3W (FR4) / 41.7°C/W — no RθJA row published |
| Body diode VSD / IS | 1.2V max / 3.9A — no trr published |
| EAS avalanche | No numeric row in v1.1 |
| TJ range | -55°C to 150°C |
The number to memorize is 3W. Conduction alone at the 3.9A sticker burns 1.2W — 40% of the budget — and switching loss eats the rest. This is a switch for a few hundred milliamps to a couple of amps, not a pass element.
How the 3W budget disappears at the sticker ratings:
Run the sticker current at 500kHz and the two losses alone consume ~90% of the budget. Design to the 3W ceiling — that is the real specification of this package.
Wire it by function: pins 5–8 (drain) take the switched node, pins 1–3 (source) return to ground, pin 4 (gate) gets 10V drive. The catch diode D1 sits across the load, cathode on the bus — never across the FET.
Two details matter at 200V: the drain node is live at full bus potential when the FET is off (respect creepage and keep it away from the gate path), and the gate needs a true 10V driver — a 3.3V or 5V GPIO leaves the channel half-enhanced with no guaranteed resistance.
Mistake 1: Trusting a library footprint instead of the sheet. SOP-8 MOSFET pin orders vary by vendor — not every part is 1–3 source / 4 gate / 5–8 drain.
Why does it matter? A swapped drain and source forward-biases the body diode, and the load never turns off.
Check the footprint against the NCE v1.1 drawing, then verify with diode mode across pins 1–3 and 5–8: one diode drop in one polarity only.
Mistake 2: Long, skinny gate traces with a big loop area. Gate-loop inductance rings against the input capacitance — forum cases describe 20nH (about 2cm of track) causing enough ringing to fire the gate.
Why does it matter here? At 200V, dv/dt couples through Cgd (75pF reverse transfer) and the ringing lifts the gate toward the 3V threshold.
Keep driver-to-gate short and wide, pair the return path beside it, and place the driver within a few centimeters — TI's layout notes on gate-drive routing cover exactly this.
Mistake 3: Letting the gate float at power-up. No pull-down means leakage or noise decides the gate voltage.
What does a floating gate do to your load at 200V? It turns the FET on whenever the charge builds up — with the full bus behind it.
A 10k pull-down from gate to source holds the channel off while the driver boots.
Mistake 4: Driving from 3.3V or 5V and expecting 79mΩ. The threshold is 2–4V (typ 3V), so 5V conducts — but resistance is guaranteed at 10V only.
The honest result: a half-enhanced channel runs hotter and slower than the sheet promises, and the 3W budget shrinks fast.
Use a 10V driver or a bootstrap stage; this is not a logic-level part.
Mistake 5: Treating the 3W budget as headroom instead of the ceiling. At the 3.9A sticker, conduction alone is 1.2W — 40% of everything the package can shed.
With no exposed pad, the heat leaves through the leads and the board copper. Honest continuous duty is around 2–2.5A on a well-poured board, less in a warm enclosure.
Pour copper on pins 1–3 and 5–8, stitch vias, and keep hot neighbors away.
Mistake 6: Routing the switching node over or beside the gate path. Trace-to-trace coupling creates capacitor plates — the 200V drain node injects charge straight into a high-impedance gate.
Forum guidance is blunt: don't stack switching traces over gate traces on adjacent layers, and keep the drain-side copper off the gate return.
Route the gate as a quiet pair, then let the drain node own its own space with proper creepage for 200V.
ICMASS stocks the NCE0203S in tape and reel, tested at the datasheet conditions: RDS(on) 79mΩ max at 10V/3.7A. Same-day shipping from Shenzhen; the 200V shelf — NCE0203S, NCE0208KA (TO-252), NCE0240 (TO-220) — is on one row for the step-up.
A: Pins 1–3 source, pin 4 gate, pins 5–8 drain. The part is a 200V/3.9A N-channel trench MOSFET in SOP-8 with marking “0203” and the pin-1 dot at the top left. This is the standard NCE SOP-8 order, but confirm against the v1.1 drawing before reusing a library footprint.
A: Only if the pin order matches — not all SOP-8 MOSFETs are 1–3 S / 4 G / 5–8 D. A drain-source swap forward-biases the body diode and the load never turns off. Check both datasheets, then do a diode-mode measurement across the source and drain groups before power-up.
A: Check for a drain-source swap or a floating gate. If the drain group is on the ground side, the body diode conducts permanently regardless of drive. If the gate has no pull-down, leakage or noise charges it above the 3V-typ threshold and the FET conducts on its own.
A: It conducts, but there is no resistance guarantee below 10V. Threshold sits at 2–4V, so 5V turns the channel on for light loads. For the guaranteed 79mΩ max, use a 10V driver — a half-enhanced channel runs hot against the 3W budget.
A: Around 2–2.5A on a well-poured board. The 3.9A sticker burns 1.2W of the 3W budget before switching losses start; the 100°C row says 2.8A; and with no exposed pad the leads and board copper do all the cooling. Use it as a switch, not a pass element.
A: Yes, but note the test point: v1.1 measures at VDS = 25V. Capacitance falls steeply as drain voltage rises, and many NCE sheets measure at 100V — so don't compare this number across parts with different test points. The cleaner cross-part number is gate charge: 38nC at 10V.
A: The leads are the heatsink. Pour copper on the source pins (1–3) and the drain pins (5–8) — drain owns four of the eight pins, so most heat exits there — stitch vias to the far side, and keep hot components away. RθJC 41.7°C/W means the board does the work.
A: Marking plus a bench check. Genuine parts carry “0203” and hold 79mΩ max at 10V/3.7A. The VBsemi NCE0203S-VB carries a similar code with a different die (5A-class per its own sheet), so verify the datasheet header and measure RDS(on) when origin matters. We stock genuine NCE and test every lot at the published condition.





